1. Field of the Invention
The present invention relates generally to latches used in computer related circuitry, and more particularly to solutions for noise problems on latch output lines.
2. Description of Related Art
Fine-grain pipelining of dynamic data paths with delayed clocks requires that each dynamic gate acts as a storage element that holds the data until the next stage is finished evaluating. At the same time, the dynamic gate must be able to precharge and evaluate in the short cycle time provided.
The two demands placed on the dynamic gates often conflict. For example, when using domino logic, the demand that the output signal be held until the next stage evaluates requires that precharge on the dynamic gate be delayed so that the high output signal does not go low before the next stage dynamic gate is done discharging. This places a requirement that either the next stage must evaluate fast to reduce the hold time on its input, or that the current stage must wait to precharge, to meet the next stage input hold time requirement.
Both approaches add significant design costs. Delaying precharge on a dynamic gate means that it has less time to precharge, requiring larger precharge transistors to meet cycle time. Reducing hold time on the input of a dynamic gate requires that the dynamic gate be able to evaluate faster, requiring that either the pulldown stack be sized up, or a less complex gate be used.
Additionally, since complex gates have a higher delay time from the rising clock signal to domino output signal, a dynamic gate needs to wait until its evaluation is finished, plus hold the output long enough to make sure that next stage evaluation goes through, before the dynamic gate goes back into precharge. This restricts the use of complex gates with regular pipelined domino, and could potentially increase latency, since some low latency dynamic designs require that complex gates be used.
A possible solution is using a staticizer latch instead of an inverter as the static stage of the domino gate. For example, current semi-dynamic flip flop implementations such as a hybrid latch flip-flop 100 (FIG. 1A) or a semi-dynamic flip-flop 150 (FIG. 1B) use a dynamic pulldown stack followed in series by a staticizer latch 101 and 151, respectively, which drives storage element 102, 152, respectively, followed in series with an output driver (inverter) 103, 153, respectively. These configurations provided a three gate delay worst case clock-to-output terminal delay when the input signal was a high level, e.g., one, and the output signal transitioned from a high level to a low level, e.g., transitions from a one to a zero.
The burden of holding the output signal was placed on staticizer 101, 151, so that the dynamic stage could start precharging as soon as the dynamic stage was done evaluating and the output signal propagated through staticizer 101, 151. This removed the constraint of having to wait for the next stage to evaluate before the current stage could go into precharge.
However, the output signal from staticizer 101, 151 was now dynamic and floating during precharge. This required that a keeper 102, 152 be provided on the staticizer output node to hold the state during precharge. Keeper 102, 152 could be disabled during transitions so that staticizer 101, 151 did not have to fight keeper 102, 152 during evaluation. However, if inverters 103, 153 were eliminated to remove a gate delay, noise on the output line also could potentially propagate through keeper 101, 151 and flip the state of the output signal. Thus, inverters 103 and 153 were needed for noise immunity.